完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tsai, KH | en_US |
dc.contributor.author | Wang, DW | en_US |
dc.contributor.author | Hwang, F | en_US |
dc.date.accessioned | 2014-12-08T15:43:44Z | - |
dc.date.available | 2014-12-08T15:43:44Z | - |
dc.date.issued | 2001-06-28 | en_US |
dc.identifier.issn | 0304-3975 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/S0304-3975(00)00147-X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/29562 | - |
dc.description.abstract | The 3-stage Clos network is generally considered the most basic multistage interconnecting network (MIN). The nonblocking property of such network has been extensively studied in the past. However, there are only a few lower bound results regarding wide-sense nonblocking. We show that in the classical circuit switching environment, to guarantee wide-sense nonblocking for large r, 2n - 1 center switches are necessary, where I is the number of input switches and n is the number of inlets of each input switch. For the multirate environment, we show that for large r, any 3-stage Clos network needs atleast 3n - 2 center switches to guarantee wide-sense nonblocking. Our proof works even for the two-rate environment. (C) 2001 Elsevier Science B.V. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Lower bounds for wide-sense nonblocking Clos network | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.doi | 10.1016/S0304-3975(00)00147-X | en_US |
dc.identifier.journal | THEORETICAL COMPUTER SCIENCE | en_US |
dc.citation.volume | 261 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 323 | en_US |
dc.citation.epage | 328 | en_US |
dc.contributor.department | 應用數學系 | zh_TW |
dc.contributor.department | Department of Applied Mathematics | en_US |
dc.identifier.wosnumber | WOS:000169541100009 | - |
顯示於類別: | 會議論文 |