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dc.contributor.authorChang, KMen_US
dc.contributor.authorChung, YHen_US
dc.contributor.authorLee, TCen_US
dc.contributor.authorSun, YLen_US
dc.date.accessioned2014-12-08T15:43:49Z-
dc.date.available2014-12-08T15:43:49Z-
dc.date.issued2001-06-01en_US
dc.identifier.issn1099-0062en_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.1370416en_US
dc.identifier.urihttp://hdl.handle.net/11536/29625-
dc.description.abstractIn this study, a new method to characterize the n(+)-polysilicon/oxide interface trap state by measuring the gate voltage-gate leakage current (Vg-Jg) characteristics under the low electric field is developed. These traps are neutral and consist of the fast and slow trap states located near the Fermi level of the n(+)-polyoxide. We use the first order rate equation to characterize the relationship between the gate leakage current and the gate voltage sweep rate. A simple formula to characterize the detrapping behavior of the slow trap states with the detrapping time constant was derived. It is important to find that the smaller detrapping time constant observed in a thinner oxide (2.5 nm) is due to the field enhanced detrapping effect. (C) 2001 The Electrochemical Society.en_US
dc.language.isoen_USen_US
dc.titleA method to characterize n(+)-polysilicon/oxide interface traps in ultrathin oxidesen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/1.1370416en_US
dc.identifier.journalELECTROCHEMICAL AND SOLID STATE LETTERSen_US
dc.citation.volume4en_US
dc.citation.issue6en_US
dc.citation.spageG47en_US
dc.citation.epageG49en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000168107000012-
dc.citation.woscount2-
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