New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistors

Abstract

In this study, width-dependent hot-carrier degradation in the p-channel metal-oxide-semiconductor held-effect transistors (p-MOSFETs) with shallow-trench-isolation (STI) is presented. Results show an enhanced drain current degradation with reducing the gate width. A new model and mechanism are proposed to explain the width-dependent hot-carrier (HC) degradation for p-MOSFETs. Based on a two-dimensional channel shortening concept, a new model is developed. The mechanical stress enhanced oxide damage at the STI edge, which will induce channel shortening, is the dominant mechanism for the drain current degradation of the devices after hot-carrier stress. This is a crucial issue for present and future complementary metaloxide semiconductor (CMOS) ultra-large-scale integration (ULSI), and in particular for high-density dynamic random-access memory (DRAM), fabricated using STI technologies.