完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, JW | en_US |
dc.contributor.author | Lee, CL | en_US |
dc.contributor.author | Su, CC | en_US |
dc.contributor.author | Chen, JE | en_US |
dc.date.accessioned | 2014-12-08T15:44:22Z | - |
dc.date.available | 2014-12-08T15:44:22Z | - |
dc.date.issued | 2001 | en_US |
dc.identifier.issn | 0923-8174 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/29968 | - |
dc.identifier.uri | http://dx.doi.org/10.1023/A:1012816621144 | en_US |
dc.description.abstract | This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs "diagnosing evaluators," which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as active faults in OP's. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | fault diagnosis | en_US |
dc.subject | signal flow graph | en_US |
dc.subject | diagnosing evaluators | en_US |
dc.subject | un-powered network | en_US |
dc.title | Fault diagnosis for linear analog circuits | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1023/A:1012816621144 | en_US |
dc.identifier.journal | JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | en_US |
dc.citation.volume | 17 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 483 | en_US |
dc.citation.epage | 494 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000172279100003 | - |
dc.citation.woscount | 4 | - |
顯示於類別: | 期刊論文 |