A new method for constructing IP level power model based on power sensitivity

Abstract

As the function uf a system getting more complex. IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of tilt ir IP blocks a secret. An IP level power model is a model that takes only the primary) input statistics its parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method, fur power models based oil power sensitivities. BS analyzing the relationship between the dynamic power consumption uf CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis. the first nominal point is selected to minimize the average Estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can he applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby. it is a promising method for IP level power model construction.