矽智產設計的功率估測方法之研究

Abstract

在這篇論文中，我們針對組合邏輯電路的矽智產單元提出了一系列的功率消耗估測方法及功率消耗模型。因為矽智產供應商為了保護他們的設計概念可能只提供矽智產使用者有限的設計資訊，因此我們對應電晶體層級、閘層級以及功能層級之電路設計資訊提出不同的功率消耗估測方法及功率消耗模型。 針對提供電晶體層級設計資訊的複雜數位電路，矽智產使用者可以採用電晶體層級的模擬估測功率消耗，而圖樣壓縮法已經被採用來加速電晶體層級的功率消耗之估測。在此，我們提出單一序列取樣法減少了傳統圖樣壓縮方法採用的隨機取樣法中無用的圖樣轉換，達到改進傳統圖樣壓縮的效果。並更進一步提出多序列取樣法改善單一序列取樣法過度取樣的缺點。 針對只提供閘層級設計資訊的電路，我們提出一個較小的功率消耗模型。這個功率消耗模型只須要使用輸入信號轉換時電路的零延遲充電及放電電容值當索引就可對照出實際功率消耗的估測值。因此矽智產使用者只要使用閘層級模擬時得到的零延遲充電及放電電容值就可以查表得到實際功率消耗的估測值。在這個方法中我們採用了分群的方法減小對照表，並利用蒙地卡羅模擬法縮短了建立對照表的時間。根據實驗結果顯示，這個功率模型針對不同的輸入信號序列依然具有高度的準確性。 如果矽智產供應商只願意提供功能層級的設計資訊，則矽智產使用者只能獲得電路輸入及輸出的對應關係。我們針對這種應用提出一個採用類神經網路建立的全新功率消耗模型。假如矽智產供應商提供這樣的功率消耗模型，則矽智產使用者只須要使用功能層級模擬得到的電路輸入及輸出資訊就可以推估電路之功率消耗值。如同實驗結果所顯示，這個功率消耗模型同時具有低複雜度及高準確度的優點。

In this dissertation, we develop several power estimation and power modeling methods for combinational IPs. Because IP vendors may release only limited design information to protect their knowledge, we propose corresponding methods for the designs with only transistor-level, gate-level and function-level design information. For complex digital circuits with transistor-level design information, users can estimation the power consumption of designs using transistor-level simulation. In order to reduce the simulation time on transistor-level simulation, we propose a single-sequence sampling approach to improve the performance of vector compaction techniques by reducing the useless transitions in random sampling techniques. A multi-sequence sampling approach is also proposed to improve the over sampling problem in the single-sequence sampling approach. For the designs with only gate-level design information, we propose a smaller power model approach that only needs a 1-diemension lookup table for each design to map the zero-delay charging and discharging capacitance (CDC) during an input pattern transition to an estimative value of real power consumption. Therefore, IP users can estimate the power consumption according to the CDC values obtained from gate-level simulation. The dynamic grouping method is applied to reduce the size of lookup tables for circuits and Monte-Carlo simulation strategy is applied to reduce the characterization time. The experimental results show that our power model still has high accuracy for different input sequences. If IP vendors only provide the function-level design information, we propose a novel power model based on neural network that only requires the input and output information of each IP. If IP vendors provide such a power model, IP users can estimation the power consumption of IPs with only input and output information under a function-level simulation. As shown in the experimental results, our power model can have much smaller size with better accuracy.