以分組的輸入訊號特性為基礎的樣本壓縮技術

Abstract

在CMOS數位電路的設計上，功率的測量已成為一個重要的考量。然而，電路功率的消耗是隨著輸入樣本的不同而相異。為了準確估測出電路的功率，往往需要花費許多時間模擬全部樣本的功率消耗情形。在本篇論文中，我們提出了一個很有效率的方法。利用電路的功率靈敏度和樣本的漢明距離，我們將原來的樣本區隔成數個小集合，並且產生一個長度較短的樣本。之後，我們可以利用這個壓縮後的樣本取代原來的樣本輸入到電晶體層級的功率模擬器中得到一個估測出的功率值。由實驗的結果發現，我們的方法可以達到相當高的壓縮比，而且準確度也很不錯。

Accurate power estimation is important for low power digital CMOS circuit design. However, power dissipation is input pattern dependent. To obtain accurate power estimation, a large input sequence must be used. However, this leads to very long simulation time. In this thesis, we present an effective technique, which is based on the power sensitivity and Hamming distance, for the compaction of input sequence. According to this technique, we divide the input sequence into several subsets and generate a compact one that is much smaller than the original sequence. The estimated power dissipation is obtained by simulating the compact sequence with an accurate transistor-level power simulator. As the experimental results demonstrate, this approach achieves a high compaction ratio within reasonable loss in the accuracy of power estimation.