完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTsui, BYen_US
dc.contributor.authorLin, SSen_US
dc.contributor.authorTsai, CSen_US
dc.contributor.authorHsia, CCen_US
dc.date.accessioned2014-12-08T15:44:33Z-
dc.date.available2014-12-08T15:44:33Z-
dc.date.issued2000-12-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://hdl.handle.net/11536/30078-
dc.description.abstractPlasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler-Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully. (C) 2000 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titlePlasma charging damage during contact hole etch in high-density plasma etcheren_US
dc.typeArticleen_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume40en_US
dc.citation.issue12en_US
dc.citation.spage2039en_US
dc.citation.epage2046en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000165343100007-
dc.citation.woscount3-
顯示於類別:期刊論文


文件中的檔案:

  1. 000165343100007.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。