完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tsui, BY | en_US |
dc.contributor.author | Lin, SS | en_US |
dc.contributor.author | Tsai, CS | en_US |
dc.contributor.author | Hsia, CC | en_US |
dc.date.accessioned | 2014-12-08T15:44:33Z | - |
dc.date.available | 2014-12-08T15:44:33Z | - |
dc.date.issued | 2000-12-01 | en_US |
dc.identifier.issn | 0026-2714 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30078 | - |
dc.description.abstract | Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler-Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully. (C) 2000 Elsevier Science Ltd. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Plasma charging damage during contact hole etch in high-density plasma etcher | en_US |
dc.type | Article | en_US |
dc.identifier.journal | MICROELECTRONICS RELIABILITY | en_US |
dc.citation.volume | 40 | en_US |
dc.citation.issue | 12 | en_US |
dc.citation.spage | 2039 | en_US |
dc.citation.epage | 2046 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000165343100007 | - |
dc.citation.woscount | 3 | - |
顯示於類別: | 期刊論文 |