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dc.contributor.authorShieh, BJen_US
dc.contributor.authorLee, YSen_US
dc.contributor.authorLee, CYen_US
dc.date.accessioned2014-12-08T15:44:35Z-
dc.date.available2014-12-08T15:44:35Z-
dc.date.issued2000-12-01en_US
dc.identifier.issn1051-8215en_US
dc.identifier.urihttp://dx.doi.org/10.1109/76.889063en_US
dc.identifier.urihttp://hdl.handle.net/11536/30100-
dc.description.abstractIn this paper, we present a high-throughput memory-based VLC decoder with codeword boundary prediction, The required information for prediction is added to the proposed branch models, Based on an efficient scheme, these branch models and the Huffman free structure are mapped onto memory modules, Taking the prediction information, the decompression scheme can determine the codeword length before the decoding procedure is completed. Therefore, a parallel-processor architecture can be applied to the VLC decoder to enhance the system performance. With a clock rate of 100 MHz, a dual-processor decoding process can achieve decompression rate up to 72.5 Msymbols/s on the average. Consequently, the proposed VLC decompression scheme meets the requirements of current and advanced multimedia applications.en_US
dc.language.isoen_USen_US
dc.subjectcodeword boundary predictionen_US
dc.subjectHuffman codingen_US
dc.subjectmemory-baseden_US
dc.subjectVLDen_US
dc.titleA high-throughput memory-based VLC decoder with codeword boundary predictionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/76.889063en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGYen_US
dc.citation.volume10en_US
dc.citation.issue8en_US
dc.citation.spage1514en_US
dc.citation.epage1521en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000165834300016-
dc.citation.woscount1-
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