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dc.contributor.authorLiang, BSen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:44:56Z-
dc.date.available2014-12-08T15:44:56Z-
dc.date.issued2000-08-01en_US
dc.identifier.issn0098-3063en_US
dc.identifier.urihttp://dx.doi.org/10.1109/30.883440en_US
dc.identifier.urihttp://hdl.handle.net/11536/30343-
dc.description.abstractA new architecture is proposed to realize 3-D graphics rendering for embedded multimedia system. Because only 20% to 83% triangles in original 3-D object models are visible by simulation, our architecture is designed to eliminate the redundant operations on invisible triangles without image quality loss. It bases on our index rendering and enhanced deferred lighting approaches, and its feature is dual pipeline rendering architecture. The simulation and analysis results show that this architecture can save up to 63.4% CPU operations compared with traditional architectures.en_US
dc.language.isoen_USen_US
dc.titleComputation-effective 3-D graphics rendering architecture for embedded multimedia systemen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/30.883440en_US
dc.identifier.journalIEEE TRANSACTIONS ON CONSUMER ELECTRONICSen_US
dc.citation.volume46en_US
dc.citation.issue3en_US
dc.citation.spage735en_US
dc.citation.epage743en_US
dc.contributor.department电子工程学系及电子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000089667900044-
dc.citation.woscount0-
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