完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Zan, HW | en_US |
dc.contributor.author | Shih, PS | en_US |
dc.contributor.author | Chang, TC | en_US |
dc.contributor.author | Chang, CY | en_US |
dc.date.accessioned | 2014-12-08T15:44:56Z | - |
dc.date.available | 2014-12-08T15:44:56Z | - |
dc.date.issued | 2000-08-01 | en_US |
dc.identifier.issn | 0026-2714 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30346 | - |
dc.description.abstract | We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I-min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated SI-H bonds. (C) 2000 Elsevier Science Ltd. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Dimensional effects on the reliability of polycrystalline silicon thin-film transistors | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.journal | MICROELECTRONICS RELIABILITY | en_US |
dc.citation.volume | 40 | en_US |
dc.citation.issue | 8-10 | en_US |
dc.citation.spage | 1479 | en_US |
dc.citation.epage | 1483 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000089532800040 | - |
顯示於類別: | 會議論文 |