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dc.contributor.authorZan, HWen_US
dc.contributor.authorShih, PSen_US
dc.contributor.authorChang, TCen_US
dc.contributor.authorChang, CYen_US
dc.date.accessioned2014-12-08T15:44:56Z-
dc.date.available2014-12-08T15:44:56Z-
dc.date.issued2000-08-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://hdl.handle.net/11536/30346-
dc.description.abstractWe found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I-min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated SI-H bonds. (C) 2000 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleDimensional effects on the reliability of polycrystalline silicon thin-film transistorsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume40en_US
dc.citation.issue8-10en_US
dc.citation.spage1479en_US
dc.citation.epage1483en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000089532800040-
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