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dc.contributor.authorYeh, WCen_US
dc.contributor.authorJen, CWen_US
dc.date.accessioned2014-12-08T15:45:04Z-
dc.date.available2014-12-08T15:45:04Z-
dc.date.issued2000-07-01en_US
dc.identifier.issn0018-9340en_US
dc.identifier.urihttp://hdl.handle.net/11536/30400-
dc.description.abstractThis paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.en_US
dc.language.isoen_USen_US
dc.subjectfinal adderen_US
dc.subjectBooth encodingen_US
dc.subjectmultiple-level conditional-sum adderen_US
dc.subjectand parallel multiplieren_US
dc.titleHigh-speed booth encoded parallel multiplier designen_US
dc.typeArticleen_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTERSen_US
dc.citation.volume49en_US
dc.citation.issue7en_US
dc.citation.spage692en_US
dc.citation.epage701en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000088843800008-
dc.citation.woscount61-
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