An automatic controller extractor for HDL descriptions at the RTL

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DC 欄位	值	語言
dc.contributor.author	Liu, CNJ	en_US
dc.contributor.author	Jou, JY	en_US
dc.date.accessioned	2014-12-08T15:45:10Z	-
dc.date.available	2014-12-08T15:45:10Z	-
dc.date.issued	2000-07-01	en_US
dc.identifier.issn	0740-7475	en_US
dc.identifier.uri	http://hdl.handle.net/11536/30448	-
dc.description.abstract	Extracting controlling finite-state machines can significantly reduce state space and thereby speed functional verification. The controller extraction algorithm uses an approach that frees it from restrictions on HDL code writing style.	en_US
dc.language.iso	en_US	en_US
dc.title	An automatic controller extractor for HDL descriptions at the RTL	en_US
dc.type	Article	en_US
dc.identifier.journal	IEEE DESIGN & TEST OF COMPUTERS	en_US
dc.citation.volume	17	en_US
dc.citation.issue	3	en_US
dc.citation.spage	72	en_US
dc.citation.epage	77	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000088988700016	-
dc.citation.woscount	6	-
顯示於類別：	期刊論文

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