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dc.contributor.authorTseng, WDen_US
dc.contributor.authorWang, Ken_US
dc.date.accessioned2014-12-08T15:45:29Z-
dc.date.available2014-12-08T15:45:29Z-
dc.date.issued2000-04-01en_US
dc.identifier.issn1350-2409en_US
dc.identifier.urihttp://dx.doi.org/10.1049/ip-cds:19990198en_US
dc.identifier.urihttp://hdl.handle.net/11536/30622-
dc.description.abstractThe authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault covet-age, lest methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also formulated and analysed to support the effectiveness of the model.en_US
dc.language.isoen_USen_US
dc.titleFault coverage and defect level estimation models for partially testable MCMsen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/ip-cds:19990198en_US
dc.identifier.journalIEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMSen_US
dc.citation.volume147en_US
dc.citation.issue2en_US
dc.citation.spage119en_US
dc.citation.epage124en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000087175900004-
dc.citation.woscount0-
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