完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tseng, WD | en_US |
dc.contributor.author | Wang, K | en_US |
dc.date.accessioned | 2014-12-08T15:45:29Z | - |
dc.date.available | 2014-12-08T15:45:29Z | - |
dc.date.issued | 2000-04-01 | en_US |
dc.identifier.issn | 1350-2409 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1049/ip-cds:19990198 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30622 | - |
dc.description.abstract | The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault covet-age, lest methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also formulated and analysed to support the effectiveness of the model. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Fault coverage and defect level estimation models for partially testable MCMs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1049/ip-cds:19990198 | en_US |
dc.identifier.journal | IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | en_US |
dc.citation.volume | 147 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 119 | en_US |
dc.citation.epage | 124 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000087175900004 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |