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dc.contributor.authorTsai, WCen_US
dc.contributor.authorShung, CBen_US
dc.contributor.authorWang, SJen_US
dc.date.accessioned2014-12-08T15:45:42Z-
dc.date.available2014-12-08T15:45:42Z-
dc.date.issued2000-02-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/92.820767en_US
dc.identifier.urihttp://hdl.handle.net/11536/30741-
dc.description.abstractThis article presents two systolic architectures to speed up the computation of modular multiplication in RSA cryptosystems. In the double-layer architecture, the main operation of Montgomery's algorithm is partitioned into two parallel operations after using the precomputation of the quotient bit. In the non-interlaced architecture, we eliminate the one-clock-cycle gap between iterations by pairing off the double-layer architecture. We compare our architectures with some previously proposed Montgomery-based systolic architectures, on the basis of both modular multiplication and modular exponentiation. The comparisons indicate that our architectures offer the highest speed, lower hardware complexity, and lower power consumption.en_US
dc.language.isoen_USen_US
dc.subjectcryptosystemsen_US
dc.subjectmontgomeryen_US
dc.subjectRSAen_US
dc.subjectsystolicen_US
dc.titleTwo systolic architectures for modular multiplicationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/92.820767en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume8en_US
dc.citation.issue1en_US
dc.citation.spage103en_US
dc.citation.epage107en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000085569400012-
dc.citation.woscount27-
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