標題: | Internet-based hierarchical floorplan design |
作者: | Lin, JH Jou, JY Jiang, IHR 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | internet;floorplanning |
公開日期: | 1-十一月-1999 |
摘要: | With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA). |
URI: | http://hdl.handle.net/11536/30973 |
ISSN: | 0916-8508 |
期刊: | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Volume: | E82A |
Issue: | 11 |
起始頁: | 2414 |
結束頁: | 2423 |
顯示於類別: | 期刊論文 |