Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs

Abstract

The multiplier-free design of transforms implemented in LUT-based FPGAs is presented. To fit bit-level grain size in the FPGA device at algorithm level the authors use modified distributed arithmetic (DA) and a named adder-based DA to formulate bit-level transform expressions, then they further minimise hardware cost by the proposed vertical subexpression sharing. For implementation, the required input buffer design is also considered by employing FPGA device characteristics and cyclic formulation. The proposed design can offer savings in excess of two-thirds of hardware cost compared with ROM-based DA.