A fault-tolerant architecture for ATM networks

Abstract

The asynchronous transfer mode (ATM) is the transfer mode recommended for the broad integrated service digital network (B-ISDN) by ITU-T. In this paper, we propose a self-routing fault-tolerant switching architecture for ATM networks. The proposed architecture uses subswitches and extra links to provide alternative paths; hence, can tolerate multiple faults. Analytical results show that the total number of redundant paths increases exponentially as the size of the network increases. A simulation model is developed. Simulation results indicate that the proposed architecture is much more fault-tolerant and cost-effective than those architectures found in the literature. Simulation results also illustrate that the proposed architecture still maintains a high throughput with an acceptable cell delay time, even when the number of faulty elements increases. (C) 1999 Elsevier Science B.V. All rights reserved.