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dc.contributor.authorLin, Yi-Kaien_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorLiao, Yen-Chinen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2014-12-08T15:46:10Z-
dc.date.available2014-12-08T15:46:10Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2078-0en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/31042-
dc.description.abstractProgressive edge-growth (PEG) algorithm was proven to be a simple and effective approach to design good LDPC codes. However, the Tanner graph constructed by PEG algorithm is non-structured which leads the positions of 1's of the corresponding parity check matrix fully random. In this paper, we propose a general method based on PEG algorithm to construct structured Tanner graphs. These hardware-oriented LDPC codes can reduce the VLSI implementation complexity. Similar to PEG method, our CP-PEG approach can be used to construct both regular and irregular Tanner graphs with flexible parameters. For the consideration of encoding complexity and error floor, the modifications of proposed algorithm are discussed. Simulation results show that our codes, in terms of bit error rate (BER) or packet error rate (PER), outperform other PEG-based LDPC codes and are better than the codes in IEEE 802.16e.en_US
dc.language.isoen_USen_US
dc.titleStructured LDPC codes with low error floor based on PEG Tanner graphsen_US
dc.typeArticleen_US
dc.identifier.journalPROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10en_US
dc.citation.spage1846en_US
dc.citation.epage1849en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000258532101193-
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