完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, CY | en_US |
dc.contributor.author | Jiang, HC | en_US |
dc.date.accessioned | 2014-12-08T15:46:30Z | - |
dc.date.available | 2014-12-08T15:46:30Z | - |
dc.date.issued | 1999-06-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/92.766751 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31290 | - |
dc.description.abstract | An improved bipolar junction transistor (BJT) based silicon retina with simple and compact structure is proposed and analyzed, In the proposed structure, the BJT smoothing network, which models the layer of horizontal cells in the vertebrate retina, is implemented by placing enhancement n-channel MOSFET's among the bases of parasitic BJT's existing in a CMOS process to form an unique and compact structure. Thus, the smoothing characteristics can be tuned in a wide range. Moreover, an extra emitter is incorporated with each BJT at the pixel to act as the row switch. This reduces the cell area of the silicon retina and increases the resolution. Using the proposed new structure, an experimental 64 x 64 BJT-based silicon retina chip has been fabricated by using 0.5-mu m CMOS technology. The measurement results on the tunability of the smooth area in the smoothing network as well as the dynamic characteristics of the proposed silicon retina in detecting moving objects have been presented. It is believed that the improved structure is very suitable for the very large scale integration implementation of the retina and its application systems for CMOS smart sensors. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | adaptive smoothing function | en_US |
dc.subject | BJT-based silicon retina | en_US |
dc.subject | BJT smoothing network | en_US |
dc.subject | CMOS smart sensor | en_US |
dc.subject | tunable smooth area | en_US |
dc.subject | VLSI | en_US |
dc.title | An improved BJT-based silicon retina with tunable image smoothing capability | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/92.766751 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 7 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 241 | en_US |
dc.citation.epage | 248 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000080579700010 | - |
dc.citation.woscount | 19 | - |
顯示於類別: | 期刊論文 |