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dc.contributor.authorLee, YSen_US
dc.contributor.authorShieh, BJen_US
dc.contributor.authorLee, CYen_US
dc.date.accessioned2014-12-08T15:46:34Z-
dc.date.available2014-12-08T15:46:34Z-
dc.date.issued1999-06-01en_US
dc.identifier.issn1057-7130en_US
dc.identifier.urihttp://dx.doi.org/10.1109/82.769782en_US
dc.identifier.urihttp://hdl.handle.net/11536/31318-
dc.description.abstractVariable-length code (VLC) is the most popular data-compression technique which has been used in many data-compression standards, such as JPEG, MPEG-2, and H.263, In this paper, we present a new memory-based tree-search algorithm and very large scale integration architecture for VLC decoders which can achieve very high decoding throughput performance. Different coding tables can be implemented by simply changing the contents of the memory without changing the system hardware, The coding table is mapped onto a memory whose space requirement has been minimized by using a new tree data structure and efficient memory-mapping strategy. In addition, we break the recursive dependency of iterative searching operations by predicting method. The proposed algorithm and architecture can predict the searching node and perform parallel operations. As a result, the decoding throughput rate can be enhanced to about three to eight times more than previously announced architecture. The proposed architecture mainly consists of memory modules and simple arithmetic unit. Based on 0.6-mu m single poly triple metal CMOS technology and MPEG-2 VLC table-15, the decoder system achieves average decoding throughput rate of 720 Mbits/s at 3 V and a 100-MHz clock rate.en_US
dc.language.isoen_USen_US
dc.subjectdecoding throughputen_US
dc.subjectFIFOen_US
dc.subjectH.263en_US
dc.subjectJPEGen_US
dc.subjectMPEGen_US
dc.subjecttree structureen_US
dc.subjectVLCen_US
dc.titleA generalized prediction method for modified memory-based high throughput VLC decoder designen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/82.769782en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSINGen_US
dc.citation.volume46en_US
dc.citation.issue6en_US
dc.citation.spage742en_US
dc.citation.epage754en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000080907100008-
dc.citation.woscount8-
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