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dc.contributor.authorChang, HCen_US
dc.contributor.authorShung, CBen_US
dc.date.accessioned2014-12-08T15:46:43Z-
dc.date.available2014-12-08T15:46:43Z-
dc.date.issued1999-04-01en_US
dc.identifier.issn0090-6778en_US
dc.identifier.urihttp://dx.doi.org/10.1109/26.764911en_US
dc.identifier.urihttp://hdl.handle.net/11536/31410-
dc.description.abstractWe propose a new efficient serial architecture to implement the Berlekamp-Massey algorithm, which is frequently used in BCH and Reed-Solomon decoders, An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces additional parallelism, We discover a clever scheduling of three finite-field multipliers to implement the algorithm very efficiently, Compared to a previously proposed serial Berlekamp-Massey architecture, our technique significantly reduces the latency.en_US
dc.language.isoen_USen_US
dc.subjectBose-Chaudhuri-Hacquenghem (BCH)en_US
dc.titleNew serial architecture for the Berlekamp-Massey algorithmen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1109/26.764911en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMMUNICATIONSen_US
dc.citation.volume47en_US
dc.citation.issue4en_US
dc.citation.spage481en_US
dc.citation.epage483en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000080420900001-
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