完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChen, HLen_US
dc.contributor.authorWu, CYen_US
dc.date.accessioned2014-12-08T15:46:43Z-
dc.date.available2014-12-08T15:46:43Z-
dc.date.issued1999-04-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.753706en_US
dc.identifier.urihttp://hdl.handle.net/11536/31412-
dc.description.abstractConsidering the impact-ionization mechanism occurring in the high drain-bias (V-DS) regime, a new I-V model considering the impact-ionization effect initiated by the drain-induced-grain-barrier-lowering (DIGBL) current has been established for the intrinsic n-channel poly-Si TFT, The simulation results with considering the developed impact-ionization current model are in excellent agreement with the experimental output characteristics of the intrinsic n-channel poly-Si TFT with the mask-gate length ranging from 5 mu m to 40 mu m. In resolving the physical parameters and their underlying operation mechanisms including the grain-barrier height, DIGBL current, and impact-ionization current, the developed I-V model will be beneficial to further understand the underlying physics of the intrinsic poky-Si TFT.en_US
dc.language.isoen_USen_US
dc.subjectDIGBLen_US
dc.subjectimpact-ionizationen_US
dc.subjectI-V modelen_US
dc.subjectpoly-Si TFTen_US
dc.titleA new I-V model considering the impact-ionization effect initiated by the DIGBL current for the intrinsic n-channel poly-Si TFT'sen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/16.753706en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume46en_US
dc.citation.issue4en_US
dc.citation.spage722en_US
dc.citation.epage728en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000079394700016-
dc.citation.woscount8-
顯示於類別:期刊論文


文件中的檔案:

  1. 000079394700016.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。