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dc.contributor.authorLin, CFen_US
dc.contributor.authorTseng, WTen_US
dc.contributor.authorFeng, MSen_US
dc.date.accessioned2014-12-08T15:46:44Z-
dc.date.available2014-12-08T15:46:44Z-
dc.date.issued1999-04-01en_US
dc.identifier.issn0013-4651en_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.1391796en_US
dc.identifier.urihttp://hdl.handle.net/11536/31426-
dc.description.abstractA multilayer thin film passivation structure based on alternating plasma-enhanced chemical vapor deposited (PECVD) SiOx-SiNx layers are prepared and characterized, in order to improve and optimize the electrical performance and hot carrier reliability of polyload resistors in 4-transistor (4-T) cache static random access memory devices. SiH4-N2O gas mixtures are utilized as precursors for oxide CVD process. Adopting a higher SiH4/N2O flow rate ratio during deposition renders the resulting oxide films more silicon rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics are also accompanied by enhanced resistance of polyload resistor and lower percentage hot-carrier linear drain current (I-dlin) degradation. An increase in RI from 1.46 to 1.67 translates to a rise in resistance of polyload resistor from 98 to 225 G Omega and a fall in I-dlin from 5.8 to 4.5%. Further improvement in device performance can be realized by modifying the stoichiometry of the overlying nitride passivation layer. This is achieved by increasing bias power while reducing the SiH4/NH3 gas flow rate ratio during the PECVD nitride deposition process. The nitride thus thus deposited contain lower Si-H bond density, and exhibit lower buffered oxide etch rates and compressive stress. Passivation structures based on the combination of a high RI oxide and a low Si-H content nitride layers yield the most promising device performance and reliability. Defect species in the oxide passivation layer are identified and their charge trapping mechanisms clarified. Impact of moisture and hydrogen from the passivation on polygate and load resistor are both held responsible for device degradation. Interfacial defect reactions involving both hydrogen and moisture are proposed to account for the carrier trapping mechanisms responsible for device failure. (C) 1999 The Electrochemical Society. S0013-4651(98)02-078-3. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titleOptimization of multilayer thin film passivation processes for improving cache memory device performanceen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/1.1391796en_US
dc.identifier.journalJOURNAL OF THE ELECTROCHEMICAL SOCIETYen_US
dc.citation.volume146en_US
dc.citation.issue4en_US
dc.citation.spage1510en_US
dc.citation.epage1516en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000079811000044-
dc.citation.woscount3-
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