Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, TY | en_US |
dc.contributor.author | Lei, TF | en_US |
dc.contributor.author | Chao, TS | en_US |
dc.contributor.author | Huang, CT | en_US |
dc.contributor.author | Chen, SK | en_US |
dc.contributor.author | Tuan, A | en_US |
dc.contributor.author | Chou, S | en_US |
dc.date.accessioned | 2014-12-08T15:46:44Z | - |
dc.date.available | 2014-12-08T15:46:44Z | - |
dc.date.issued | 1999-04-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.38.2243 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31433 | - |
dc.description.abstract | To get high quality ultra-thin oxide is very important and difficult for IC industry now. Using NF3 annealed poly-Si gate to improve gate oxide integrity is described. However, reducing fate, source and drain parasitic resistance with gate lengths down to 0.2 mu m is another key point. Co-salicide process can successfully reduce the gate resistance even for a gate length of 0.075 mu m. Although, Co-salicide process has a leakage problem. Using NF3 annealing to prevent Co diffusing into gate oxide is described too. Results show that the optimal NF3 annealing significantly improves electrical characteristics of ultra-thin oxide and Co-salicide process in terms of leakage current and breakdown field, as compared to the samples without NF3 annealing. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | ultra-thin oxide | en_US |
dc.subject | NF3 | en_US |
dc.subject | co-sacilide | en_US |
dc.subject | Si-F and Si-N bonds | en_US |
dc.subject | breakdown field | en_US |
dc.subject | leakage current | en_US |
dc.subject | tunneling mechanism | en_US |
dc.title | Improvement of ultra-thin 3.3 nm thick oxide for co-salicide process using NF3 annealed poly-gate | en_US |
dc.type | Article; Proceedings Paper | en_US |
dc.identifier.doi | 10.1143/JJAP.38.2243 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
dc.citation.volume | 38 | en_US |
dc.citation.issue | 4B | en_US |
dc.citation.spage | 2243 | en_US |
dc.citation.epage | 2246 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000082871300014 | - |
Appears in Collections: | Conferences Paper |
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