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dc.contributor.authorYan, JTen_US
dc.date.accessioned2014-12-08T15:47:13Z-
dc.date.available2014-12-08T15:47:13Z-
dc.date.issued1999en_US
dc.identifier.issn1065-514Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/31678-
dc.description.abstractIt is well known that standard cells have been widely used to implement VLSI circuits in the automation of physical design. Since one major aim of a cell-based design is to minimize total layout area in a standard cell placement, the number of feedthrough cells will be minimized to reduce total cell area in a standard cell placement. In this paper, first, we model a partitioning-based row assignment (PRA) problem to minimize the number of feedthrough cells in a standard cell placement. Furthermore, an integer linear programming (ILP) approach is proposed to solve the PRA problem in a standard cell placement. Finally, the ILP approach has been implemented and two standard-cell net-lists, Primary 1 and Primary 2, have been tested by the proposed approach, Bose's approach [4] and an exhaustive search approach,respectively The experimental results show that the ILP approach obtains fewer feedthrough cells than Bose's approach in a partitioning-based standard cell placement.en_US
dc.language.isoen_USen_US
dc.subjectphysical designen_US
dc.subjectplacementen_US
dc.subjectstandard cellen_US
dc.subjectfeedthrough cellen_US
dc.subjectinteger linear programmingen_US
dc.titleAn ILP formulation for minimizing the number of feedthrough cells in a standard cell placementen_US
dc.typeArticleen_US
dc.identifier.journalVLSI DESIGNen_US
dc.citation.volume10en_US
dc.citation.issue2en_US
dc.citation.spage169en_US
dc.citation.epage176en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000085196200004-
dc.citation.woscount0-
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