標題: A VLSI architecture design for dual-mode QAM and VSB digital CATV transceiver
作者: Shiue, MT
Wang, CK
Way, WI
電信工程研究所
Institute of Communications Engineering
關鍵字: QAM;VSB;AGC;carrier recovery;timing recovery;fractionally spaced blind equalizer and DFE
公開日期: 1-十二月-1998
摘要: In this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions [1], [2]. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are +/-6 kHz of carrier frequency offset, +/- 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency.
URI: http://hdl.handle.net/11536/31690
ISSN: 0916-8516
期刊: IEICE TRANSACTIONS ON COMMUNICATIONS
Volume: E81B
Issue: 12
起始頁: 2351
結束頁: 2356
顯示於類別:會議論文