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dc.contributor.authorWu, CCen_US
dc.contributor.authorChen, Cen_US
dc.date.accessioned2014-12-08T15:47:17Z-
dc.date.available2014-12-08T15:47:17Z-
dc.date.issued1998-12-01en_US
dc.identifier.issn1016-2364en_US
dc.identifier.urihttp://hdl.handle.net/11536/31726-
dc.description.abstractThe release consistency model is the generally accepted hardware-centric relaxed memory consistency model because of its performance and implementation complexity. By extending the release consistency model, in this paper. we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessor systems with parallel-multithreaded processing elements. The new model uses a new categorization for memory references and utilizes the feature of parallel multithreaded processors (PMPs). We further partition acquire and release references into three sub-categories: one for lock-unlock pairs, one for barrier synchronization, and the last for others. According to the semantic of each synchronization primitive, each sub-category has its own relaxed restrictions. On the other hand, the feature of a PMP is that it is capable of executing more than one thread at the same time, where all parallel threads share only one cache hierarchy. Under the new model, we can use dual write-caches to reduce write traffic and synchronization time. We have used five benchmarks in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, the new model is superior to the release consistency model at best by about 11%.en_US
dc.language.isoen_USen_US
dc.subjectmemory consistency modelen_US
dc.subjectmultithreaden_US
dc.subjectmultiprocessoren_US
dc.subjectwrite cacheen_US
dc.subjectsynchronizationen_US
dc.subjectPSC modelen_US
dc.subjectbarrieren_US
dc.subjectperformance evaluationen_US
dc.titleA new relaxed memory consistency model for shared-memory multiprocessors with parallel-multithreaded processing elementsen_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF INFORMATION SCIENCE AND ENGINEERINGen_US
dc.citation.volume14en_US
dc.citation.issue4en_US
dc.citation.spage785en_US
dc.citation.epage808en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000077995800006-
dc.citation.woscount1-
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