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dc.contributor.authorLiang, C. -P.en_US
dc.contributor.authorHuang, T. -J.en_US
dc.contributor.authorRao, P. -Z.en_US
dc.contributor.authorChung, S. -J.en_US
dc.date.accessioned2014-12-08T15:48:15Z-
dc.date.available2014-12-08T15:48:15Z-
dc.date.issued2010-09-30en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttp://dx.doi.org/10.1049/el.2010.1278en_US
dc.identifier.urihttp://hdl.handle.net/11536/32169-
dc.description.abstractA low-power 5.25 GHz voltage-controlled oscillator ( VCO) with phase-noise improvement is designed in a 0.18 mu m CMOS 1P6M process. Owing to the use of a larger value of parallel capacitor, an additional harmonic-suppressed capacitor, and an appropriate bulk bias voltage of transistor, a good figure of merit of - 190 dBc/Hz can be achieved without extra chip area and CMOS process steps. The fabricated VCO operates from 5.12 to 5.36 GHz with a core power consumption of 1.9 mW and active chip area of 0.15 mm(2). The measured phase noise at 1 MHz offset is about - 119 dBc/Hz.en_US
dc.language.isoen_USen_US
dc.titleLow-power VCO with phase-noise improvement in 0.18 mu m CMOS technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/el.2010.1278en_US
dc.identifier.journalELECTRONICS LETTERSen_US
dc.citation.volume46en_US
dc.citation.issue20en_US
dc.citation.spage1385en_US
dc.citation.epage1387en_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.identifier.wosnumberWOS:000282285800020-
dc.citation.woscount1-
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