Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap

doi:10.1109/TED.2010.2051248

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Watanabe, Hiroshi	en_US
dc.date.accessioned	2014-12-08T15:48:37Z	-
dc.date.available	2014-12-08T15:48:37Z	-
dc.date.issued	2010-08-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TED.2010.2051248	en_US
dc.identifier.uri	http://hdl.handle.net/11536/32336	-
dc.description.abstract	The single-electron general-purpose device simulator is improved to carry out a wide-range transient analysis from 1 ps to 10 years. We apply this simulator to a floating gate (FG) nonvolatile memory cell in order to simulate a degradation mode of data retention owing to the direct tunneling enhanced by the fixed charge stored by a local trap in an interpoly dielectric. The scaling impact of ideal high-K interpoly dielectric FG nonvolatile memory cell is also investigated.	en_US
dc.language.iso	en_US	en_US
dc.subject	Coulomb oscillation	en_US
dc.subject	device modeling	en_US
dc.subject	device simulation	en_US
dc.subject	floating gate (FG)	en_US
dc.subject	local trap	en_US
dc.subject	memory	en_US
dc.subject	modeling	en_US
dc.subject	single-electron sensitivity	en_US
dc.subject	TCAD	en_US
dc.subject	trap-assisted tunneling	en_US
dc.title	Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TED.2010.2051248	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	57	en_US
dc.citation.issue	8	en_US
dc.citation.spage	1873	en_US
dc.citation.epage	1882	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000283382800018	-
dc.citation.woscount	3	-
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