隱藏式選擇性閘極結構之薄膜電晶體記憶體元件研究

Abstract

我們首先提出一種新穎的隱藏式選擇性閘極結構薄膜電晶體記憶體元件，它的製程條件不僅簡單，也能與傳統的標準CMOS 製程相容，特別適合嵌入式非揮發性記憶體的應用。在本篇論文中，我們首次在薄膜電晶體記憶體元件中嘗試更為有效的電子注入之源極端注入方式(Source-Side-Injection)來做寫入，以及能帶能帶穿隧產生之熱電洞(BTBTHH)的機制來作為電子抹除的操作。此外，我們也同時驗證可消除二位元效應以及可在單一位元胞進行二位元的操作。值得注意的，薄膜電晶體記憶體所需較大的操作偏壓會造成較嚴重的偏壓干擾現象，包括閘極干擾和汲極干擾。不同於分離式的電荷儲存元件，懸浮閘極結構的薄膜電晶體記憶體在寫入以及抹除操作中，面臨了可能威脅到免於二位元效應特性的懸浮閘極電壓耦合效應問題。 與單純由氮化矽組成的電子捕捉層和懸浮閘極結構的元件相比，在氮化矽中加入內嵌式矽奈米晶體作為電子捕捉層的元件，經過耐久度測試後的元件，都能夠有較佳的電子保存能力(約6-8%的漏電改善)，尤其是在高溫的電子保存性量測中更為明顯。在耐久可靠度測試中，氮化矽元件以及在氮化矽中加入內嵌式矽奈米晶體作為電子捕捉層的元件有嚴重的電子電洞不匹配的問題以及在氧化矽中造成許多缺陷，這些造成元件的記憶體窗有關閉的傾向。然而對於懸浮閘極結構的記憶體元件而言，即使寫入狀態和抹除狀態的閥值電壓都會隨著測試次數增加而上升，仍然不會發生記憶體窗關閉的現象。

For the first time, we proposed the novel Wrapped-Select-Gate (WSG)SONOS-type thin film transistor (TFT) memory device. The fabrication process ofWSG structure memory device is not only simple but also compatible to conventionalstandard CMOS technology which fits for embedded non-volatile memory applications. In this thesis, we firstly apply source-side-injection (SSI) mechanism to three kinds SONOS-type thin film transistor memory and perform erase operation with Band-to-Band Tunneling Hot-Hole (BTBTHH). Furthermore, the elimination of 2nd bit effect and 2 bit per cell operation are also demonstrated in the same time. It is worth to note that higher operation voltage in TFT memory causes serious disturb phenomena including word-line disturbance and bit-line disturbance. Unlike to discrete charge trapping devices, TFT memory cell with floating gate structure have floating gate coupling concerns in every program or erase operation which may threaten the immunity to 2nd bit effect. Compared to pure nitride trapping layer and floating gate structure, nitride with embedded silicon nanocrystals (Si-NCs) as trapping layer material always has better retention characteristics (6-8% improvement) when device already suffers 10k times P/E cycle, especially in high temperature retention test. In endurance characteristics, Nitride cell and Nitride_Dot cell suffer charge mismatch problem and generation of oxide defects which gives rise to window closure phenomenon while Floating gate cell still can maintain memory window even though both threshold voltage of program state and erase state keep on a rise.