標題: A two-phase fault simulation scheme for sequential circuits
作者: Wu, WC
Lee, CL
Chen, JE
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: computer-aided-design;digital testing;sequential circuits;fault simulation;untestable faults
公開日期: 1-Sep-1998
摘要: A two-phase fault simulation scheme for sequential circuits is proposed. In this fault simulation, the input sequence is divided into two parts. In the first phase, fault free simulation is performed with the first sequence of patterns. In the second phase, fault simulation is performed with the rest of the patterns. Five cases of faults which result from two-phase fault simulation are discussed in detail. Significant speedup in simulation time can be obtained because this fault simulation approach can quickly drop Case 1 faults, which are time-consuming faults and would be considered undetectable in the traditional three-value fault simulation but are actually detected in exact fault simulation. Almost "exact" results can be obtained for detected faults except for a small percentage of over-detected-faults (ODFs) and under-detected-faults (UDFs).
URI: http://hdl.handle.net/11536/32421
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 14
Issue: 3
起始頁: 669
結束頁: 686
Appears in Collections:Articles