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dc.contributor.authorHuang, CYen_US
dc.contributor.authorChen, MJen_US
dc.date.accessioned2014-12-08T15:49:17Z-
dc.date.available2014-12-08T15:49:17Z-
dc.date.issued1998-03-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://hdl.handle.net/11536/32773-
dc.description.abstractAs temperature is lowered, behaviors of well-type guard rings in an epitaxial substrate are quite different from those at RT so that the previous formulation is unable to reflect these discrepancies precisely. This leads to a new escape-current model suitable for low-temperature applications. In addition to the structural parameters, the new model is also functions of other physical quantities such as temperature, high-level injection, surface recombination velocity at the high/low junction and minority-carrier transport parameters, which are also important at low temperature. (C) 1997 Elsevier Science Ltd.en_US
dc.language.isoen_USen_US
dc.titleA model for low-temperature operation of minority-carrier well-type guard rings in epitaxial CMOS structuresen_US
dc.typeArticleen_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume42en_US
dc.citation.issue3en_US
dc.citation.spage453en_US
dc.citation.epage457en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000073203900025-
dc.citation.woscount0-
Appears in Collections:Articles


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