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dc.contributor.authorLiang, STen_US
dc.contributor.authorYuang, MCen_US
dc.date.accessioned2014-12-08T15:49:21Z-
dc.date.available2014-12-08T15:49:21Z-
dc.date.issued1998-02-01en_US
dc.identifier.issn0916-8516en_US
dc.identifier.urihttp://hdl.handle.net/11536/32798-
dc.description.abstractAsynchronous Transfer Mode (ATM) networks are expected to support a diverse mix of traffic sources requiring different Quality Of Service (QOS) guarantees. This paper initially examines several existing scheduling disciplines which offer delay guarantees in ATM switches. Among them, the Earliest-Due-Date (EDD) discipline has been regarded as one of the most promising scheduling disciplines. The EDD discipline schedules the departure of a cell belonging to a call based on the delay priority assigned for that call during the call set-up. Supporting n delay-based service classes through the use of n respective urgency numbers D-0 to Dn-1 (D-0 less than or equal to D-1 less than or equal to...less than or equal to Dn-1), EDD allows a class-i cell to precede any class-j (j>i) cell arriving not prior to (D-j - D-i)-slot time. The main goal of the paper is to determine the urgency numbers (D-i's), based on an in-depth queueing analysis, in an attempt to offer ninety-nine percentile delay guarantees for higher priority calls under various traffic loads. In the analysis, we derive system-time distributions for both high-and low-priority cells based on a discrete-time, single-server queueing model assuming renewal and non-renewal arrival processes. The validity of the analysis is justified via simulation. With the urgency numbers (D-i's) determined, we further propose a feasible efficient VLSI implementation architecture for the EDD scheduling discipline, furnishing the realization of QOS guarantees in ATM switches.en_US
dc.language.isoen_USen_US
dc.subjectasynchronous transfer mode (ATM)en_US
dc.subjectquality of service (QOS)en_US
dc.subjectdelay priorityen_US
dc.subjectearliest-due-date (EDD) disciplineen_US
dc.subjectrenewal arrival processen_US
dc.subjectinterrupted poisson processen_US
dc.titleRealization of earliest-due-date scheduling discipline for ATM switchesen_US
dc.typeArticleen_US
dc.identifier.journalIEICE TRANSACTIONS ON COMMUNICATIONSen_US
dc.citation.volumeE81Ben_US
dc.citation.issue2en_US
dc.citation.spage363en_US
dc.citation.epage372en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000072319300029-
dc.citation.woscount0-
Appears in Collections:Articles