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dc.contributor.authorYen, Cheng-Chengen_US
dc.contributor.authorLiao, Chi-Shengen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:04:50Z-
dc.date.available2014-12-08T15:04:50Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-1616-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/3340-
dc.identifier.urihttp://dx.doi.org/10.1109/VDAT.2008.4542442en_US
dc.description.abstractA new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-mu m CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.en_US
dc.language.isoen_USen_US
dc.titleNew transient detection circuit for system-level ESD protectionen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/VDAT.2008.4542442en_US
dc.identifier.journal2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAMen_US
dc.citation.spage180en_US
dc.citation.epage183en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000256565800044-
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