完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | HSIEH, SF | en_US |
dc.contributor.author | LIU, KJR | en_US |
dc.contributor.author | YAO, K | en_US |
dc.date.accessioned | 2014-12-08T15:04:53Z | - |
dc.date.available | 2014-12-08T15:04:53Z | - |
dc.date.issued | 1992-06-01 | en_US |
dc.identifier.issn | 1057-7130 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/82.145296 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/3398 | - |
dc.description.abstract | We propose a dual-state systolic structure to perform joint up/down-dating operations encountered in windowed recursive least-squares (RLS) estimation problems. It is based on successively performing Givens rotations for updating and hyperbolic rotations for downdating. Due to data independency, a series of Givens and hyperbolic rotations can be interleaved and parallel processing can be achieved by alternatively performing updating and downdating both in time and space. This flip-flop nature of up/down-dating characterizes the feature of the dual-state systolic triarray. Efficient implementation on the evaluation of optimal residuals is also considered. This systolic architecture is promising for the VLSI implementation of fixed size sliding-window recursive least-squares estimations. | en_US |
dc.language.iso | en_US | en_US |
dc.title | DUAL-STATE SYSTOLIC ARCHITECTURES FOR UP DOWNDATING RLS ADAPTIVE FILTERING | en_US |
dc.type | Note | en_US |
dc.identifier.doi | 10.1109/82.145296 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | en_US |
dc.citation.volume | 39 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 382 | en_US |
dc.citation.epage | 385 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:A1992JD57100007 | - |
dc.citation.woscount | 3 | - |
顯示於類別: | 期刊論文 |