完整後設資料紀錄
DC 欄位語言
dc.contributor.authorCHUNG, SSSen_US
dc.contributor.authorLI, TCen_US
dc.date.accessioned2014-12-08T15:04:58Z-
dc.date.available2014-12-08T15:04:58Z-
dc.date.issued1992-03-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.123486en_US
dc.identifier.urihttp://hdl.handle.net/11536/3498-
dc.description.abstractA simple closed-form expression of the threshold voltage is developed for Trench-Isolated MOS (TIMOS) devices with feature size down to the deep-submicrometer range. The analytical expression is the first developed to include the non-uniform doping effect of a narrow-gate-width device. The inverse narrow width effect can be predicted analytically from the proposed model. It was derived by modeling the gate sidewall capacitance to include the two-dimensional field-induced edge fringing effect and solving the Poisson equation to include the channel implant effect at different operating backgate biases. A two-dimensional simulation program was also developed, and the simulated data were used for verification of the analytical model. Good agreements between the modeled and simulated data have been achieved for a wide range of gate widths and biases. The model is well suited for the design of the basic transistor cell in DRAM circuits using trench field oxide isolation structure.en_US
dc.language.isoen_USen_US
dc.titleAN ANALYTICAL THRESHOLD-VOLTAGE MODEL OF TRENCH-ISOLATED MOS DEVICES WITH NONUNIFORMLY DOPED SUBSTRATESen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/16.123486en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume39en_US
dc.citation.issue3en_US
dc.citation.spage614en_US
dc.citation.epage622en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1992HE79900023-
dc.citation.woscount18-
顯示於類別:期刊論文


文件中的檔案:

  1. A1992HE79900023.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。