標題: | Integration of modified plasma-enhanced chemical vapor deposited tetraethoxysilane intermetal dielectric and chemical-mechanical polishing processes for 0.35 mu m IC device reliability improvement |
作者: | Wang, YL Tseng, WT Feng, MS 材料科學與工程學系 電子工程學系及電子研究所 Department of Materials Science and Engineering Department of Electronics Engineering and Institute of Electronics |
關鍵字: | intermetal dielectrics;chemical-mechanical polishing (CMP);PE-TEOS;hot carriers;device reliability;moisture resistance |
公開日期: | 1-九月-1997 |
摘要: | The process of interlevel dielectrics (ILD) between poly-Si and metal is critical to device characteristics and reliability. Also, the shrinking design rules demand greater hot carrier reliability, which is strongly influenced by the ILD process. In this paper we describe a process for improving the reliability of 0.35 mu m devices by using modified plasma-enhanced chemical vapor deposited tetraethoxysilane (PECVD-TEOS) N2O-rich or O-2-rich ILD films which contain less hydrogen concentration and excellent moisture resistance, and less mobile ion penetration after chemical-mechanical polishing (CMP), relative to standard PE-TEOS oxides. The hot carrier lifetime and the held isolation device threshold voltage are monitored and compared between devices with ILD layers based on different combinations of subatomespheric O-3-TEOS borophosphorus silicate glass (BPSG), standard PE-TEOS, O-2-rich and N2O-rich oxides. The material characteristics contributing to the reduction in post-CMP mobile ion levels and the improvement in device reliability will be discussed. |
URI: | http://dx.doi.org/10.1143/JJAP.36.5492 http://hdl.handle.net/11536/350 |
ISSN: | 0021-4922 |
DOI: | 10.1143/JJAP.36.5492 |
期刊: | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS |
Volume: | 36 |
Issue: | 9A |
起始頁: | 5492 |
結束頁: | 5497 |
顯示於類別: | 期刊論文 |