BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATE

Abstract

There are arithmetic problems for the hardware realisation of bit-level median filtering algorithms. A design of a majority gate which is composed of output-wired inverters is proposed. The area and time complexities are better than the digital and analogue designs now available. This circuit is applied to a median filter design which is based on majority selection, the computation problems are thus avoided. It is a bit-sliced architecture with constant cycle time. Window shapes can be arbitrarily changed through mask-and-set modules. A median filtering system for two-dimensional image processing is presented. A binary majority gate is also an essential element in decision-making circuitry which is applied in fault-tolerant computing systems, artificial neural networks or related applications.