Title: | SWITCHED-CAPACITOR PIPELINED LOGARITHMIC A/D AND D/A CONVERTERS |
Authors: | CHENG, MH HUANG, TC 交大名義發表 電控工程研究所 National Chiao Tung University Institute of Electrical and Control Engineering |
Keywords: | CONVERTERS;CIRCUIT THEORY AND DESIGN |
Issue Date: | 1-Dec-1991 |
Abstract: | The paper presents two switched-capacitor circuits with modest complexity to implement a pipelined logarithmic digital-analogue convertor (LDAC) and logarithmic analogue-digital convertor (LADC), respectively, which spend only one clock time per conversion. In addition, the effect of the capacitor-ratio mismatch on the conversion errors of the convertor circuits is discussed. Hence, from the available maximum capacitor-ratio value and mismatch of the present integrated circuit (IC) technology, the feasible bit length of the pipelined LDAC and LADC can be computed. |
URI: | http://hdl.handle.net/11536/3615 |
ISSN: | 0956-3768 |
Journal: | IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS |
Volume: | 138 |
Issue: | 6 |
Begin Page: | 714 |
End Page: | 716 |
Appears in Collections: | Articles |
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