Title: | A HIGH-SPEED NEURAL ANALOG CIRCUIT FOR COMPUTING THE BIT-LEVEL TRANSFORM IMAGE-CODING |
Authors: | CHANG, PR HWANG, KS GONG, HM 電信工程研究所 Institute of Communications Engineering |
Issue Date: | 1-Aug-1991 |
Abstract: | This paper presents a Hopfield-type neural network approach which leads to an analog circuit for implementing the bit-level transform image. Different from the conventional digital approach to image coding, the analog coding system would operate at a much higher speed and requires less hardware than digital system. In order to utilize the concept of neural net, the computation of a two-dimensional DCT-based transform coding should be reformulated as minimizing a quadratic nonlinear programming problem subject to the corresponding 2's complement binary variables of 2-D DCT coefficients. A novel Hopfield-type neural net with a number of graded-response neurons designed to perform the quadratic nonlinear programming would lead to such a solution in a time determined by RC time constants, not by algorithmic time complexity. A fourth order Runge-Kutta simulation is conducted to verify the performance of the proposed analog circuit. Experiments show that the circuit is quite robust and independent of parameter variations and the computation time of an 8 x 8 DCT is about 1ns for RC = 10(-8). In practice, programmable hybrid digital-analog MOS circuits are required to implement the neural-based DCT optimizer. The circuit techniques are based on extremely simple and programmable analog parameterized MOS modules with such attractive features as reconfigurability, input/output compatibility, and unrestricted fan-in/fan-out capability.1 |
URI: | http://dx.doi.org/10.1109/30.85534 http://hdl.handle.net/11536/3715 |
ISSN: | 0098-3063 |
DOI: | 10.1109/30.85534 |
Journal: | IEEE TRANSACTIONS ON CONSUMER ELECTRONICS |
Volume: | 37 |
Issue: | 3 |
Begin Page: | 337 |
End Page: | 342 |
Appears in Collections: | Articles |
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