以離子植入矽化物技術製作在矽化鎳與矽介面處低溫摻雜活化的相關研究

Abstract

金屬氧化半導體元件持續微縮至奈米等級時，將會使得源極、閘極和汲極的寄生阻抗變大。因此，為了降低寄生阻抗和改善元件的性能，金屬矽化物的技術被發展在深次微米的應用上。在奈米金屬氧化半場效電晶體的製造中，矽化製程是必須的，為了抑制源極及汲極的超淺接面形成所產生的短通道效應。在本論文中，對於先進元件的製造上，淺接面的形成和熱預算的控制是很重要的。我們結合了離子植入矽化物技術製造和固態磊晶再成長的觀念去達成這兩個需求。對於金屬和矽接面的二階段金屬快速退火60秒而言，磷離子植入的試片顯現出會比硼離子植入更像是歐姆接觸。基於固態磊晶再成長摻雜物推積在介面處和離子植入矽化物技術，我們的實驗將可以達到高劑量的活化和使用低溫退火，並且結合了電流電壓和電容電壓量測法來了解固態磊晶再成長的行為。在固態磊晶再成長製程完成之後，N基底和P基底的試片隨著較高的溫度預算400℃和500℃有可能會引起缺陷的形成和摻雜物的反活化現象發生。

With the continuing scaling-down to nanometer regime of metal- oxide-semiconductor (MOS) device will increase parasitic resistance of gate, source and drain. As a result, metal silicide has been developed used in deep submicron application for reducing the parasitic resistance and to improve device performance. In nanometer MOSFET fabrication, this silicidation process requires considering to suppress short channel effect (SCE) when forming the ultra shallow source and drain junction. In this thesis, Sallow junction formation and low thermal budget control are important for advanced device manufacturing. We combined the concept of implant into silicide (IIS) and solid phase epitaxial regrowth (SPER) to achieve both requirements. For M/S junction with 2nd RTA 60s, P+ implantation samples shows more like ohmic contact behaviors than BF2+ implantation samples. Based on the IIS dopant segregation pile-up at interface and SPER, our experiment would achieve the high dosage activation and using low temperature annealing, and combine the I-V and C-V measurement to know SPER behavior. After SPER process finished, samples may cause defect formation and dopant deactivation phenomenon with higher thermal budget treatment above 450℃ for N-sub and 500℃ for P-sub.