高介電常數介電質金屬-絕緣層-金屬電容應用於動態

Abstract

隨著超大型積體電路技術的不斷發展、元件尺寸的微縮，閘極介電質的厚度必須降低以維持電容值。由國際半導體技術發展藍圖,我們發現1.5奈米製程以下，降低介電質厚度將使漏電流程呈指數級數增加。因為減低電容的厚度會增加不必要的漏電流，所以使用高介電常數的介電質可能是一種是有效的解決方法。

在本篇論文中，我們研究使用高介電常數介電值的金屬－絕緣層－金屬電容。經由適當的氮電漿處理和退火條件來改善其漏電流，得到高電容密度、低漏電流和簡單介電質製作都是使用此高介電常數介電質(TiNiO)之優點。這樣好的元件特性在未來可能被使用於射頻、類比積體電路和嵌入式系統單晶片之應用。

As the very large scale integration (VLSI) technology continues to be scaled down, the thickness of gate dielectric has to be decreased for maintaining the capacitance value and drive levels. According to ITRS road map, the decrease of dielectric thickness bellow 1.5nm will increase the leakage current exponentially. However, the high-k dielectric is considered as a solution on the issue of devices scalability.

In this thesis, we investigated the improvement on the metal-insulator-metal capacitors using a high-k dielectric combined with a plasma treatment. The high-k TiNiO dielectric shows larger capacitance density and leakage current due to crystallization after higher PDA temperature. To suppress the leakage current of crystallized dielectric, we adopted an optimized N+ plasma treatment on dielectric and the sequent post oxygen annealing. The analysis of the device characteristics in the thesis also unveil the potential of TiNiO Metal-Insulator-Metal (MIM) capacitor for future RF/analog IC application and embedded SoC.