有效成本控制的三明治型乒乓記憶體

Abstract

本研究旨在探討記憶體(緩衝器)的成本與效能上之取捨，我們提出一個適用於快速資料傳輸上的三明治型乒乓記憶體(緩衝器) ，並驗證其適切性。相對於現行之乒乓記憶體的而言，此記憶體使用較少的面積，並且在操作頻率上有更多選擇及彈性的空間。使用者可調整三明治型乒乓記憶體的容量大小，進而決定操作頻率為何，藉以有效控制成本。此外，為了測試此記憶體，我們也根據現行常用的測試演算法，發展出專屬於三明治型乒乓記憶體之測試演算法，並經由國家晶片系統設計中心，成功地完成下線並製作晶片，更進一步利用此測試演算法，偵測出一般常見的缺陷模型，結果在缺陷包容度上亦達到100%。在晶片控制單元的設計上，我們發現能使晶片控制單元所佔的面積能最小之方法。運用此方法，當減少500個記憶體單元面積的同時，亦能使額外的晶片控制單元小於500個閘數。 本研究尚依據研究結果，針對三明治型乒乓記憶體(緩衝器)實務方面之應用，以及未來之研究提出建議。

This thesis is about memory (buffer) and we present a Sandwich Ping Pong Memory. The area in the Sandwich Ping Pong Memory is much less than in a Ping Pong Memory. Besides, it is more flexible on the operation frequency compared with a Ping Pong Memory. Data are written into the Sandwich Ping Pong Memory row by row and read from it column by column simultaneously. Based on March C- algorithm, we also developed the test algorithm for the Sandwich Ping Pong Memory and named it the modified March C- algorithm. It can detect the stuck-at fault, transition fault, address fault, and coupling fault. We also successfully taped out a 64-byte Ping Pong Memory in process 0.35 2p4m in National Chip Implementation Center (CIC). Finally, we do the verification and testing. As a result, the fault coverage is at 100% of each fault. The chip is 1310 x 1100 micro meters squared. In order to design the control unit, the area overhead is under five hundred gate counts at the range of Common Bar is under 512 unit memory cells.