應用於助聽器之低功率環境噪音消除設計

Abstract

助聽器在使用時常常受到來自環境的雜訊干擾，而影響聲音的品質，但由於環境雜訊千變萬化又無法事先預測，因此在單一麥克風的處理上大致分為:使用在時域的濾波器方法以及使用在頻域的臨界值消去法。

本論文是使用頻域臨界值消去法，並在功率消耗與延遲速度之間的取捨取得一能接受的平衡。

首先在頻域的分頻方式轉換採用小波轉換(DWT) 搭配哈特利轉換(DHT)來完成，如此可各取其優點，利用小波轉換的低複雜度與哈特利轉換的低延遲度。

分頻完之後即可得到輸入訊號的頻率成份，再利用0-2k的訊號(小波訊號)來判別此輸入訊號是否為語音，接著把哈特利輸出係數減去之前紀錄的臨界值後輸出，再設定一語音保護區間，只要之後落在語音保護區間的哈特利輸出係數，不管是否判定為語音，皆視為語音來處理，此舉是為了保護連接在濁音附近的氣音，避免氣音被當成雜訊而誤判。

若分頻完的係數被判定為非語音，則將此係數衰減到近乎於零後輸出，並在環境穩定的情況下，依25%的比例更新至臨界值，目的在於雜訊臨界值的取得是利用無人講話的沉默區間所得到的訊號當成環境雜訊臨界值，如此一來雜訊臨界值將隨著環境吵雜程度而漸進式改變。

經模擬結果，可使SNR最高可改善近5db，使用台積電 0.13umCMOS製程下，總閘數約為25568，總面積約為552um*552um，功率消耗在0.16mW左右。

Speech understanding of hearing aids users are often degraded by the surrounding noise. To solve this problem, there are two approaches for single microphone hearing aids: one is the time domain filtering and the other is the spectral subtraction in the frequency domain.

In this thesis , we adopt the spectral subtraction method while try to find a acceptable tradeoff between power consumption , speech quality and processing latency.

The spectral subtraction method consists of two steps: frequency domain transformation and noise threshold selection. For frequency domain transformation, we adopt the mixed transform method by combining discrete wavelet transformation (DWT) and discrete Hartley transformation (DHT). In this way, we can take advantages of the low complexity of DWT and the low delay of DHT.

After the frequency analysis, we use the 0~2K transform signals as a measure to distinguish the voice and noise region. For a voice signal, we will subtract the noise threshold from the transformed signals. To further protect the unvoiced speech, we will set a guarded region. All signals within the guarded region are treated as voice signals to avoid over thresholding of the unvoiced signals. For a noise signal, we will degrade the transform signals to nearly zero and output the result. At the same time, the noise threshold will also be adaptively with environmental noise.

The simulation results with white noise signals show that the proposed method can improve the speech by up to 5dB.

The whole design has been implemented by Verilog and TSMC 0.13um CMOS process. The total gate count is about 25568 within 552umX552um area. The power consumption is below 0.16mW with 8KHz operating frequency.