助聽器晶片及系統---總計畫(I)

Abstract

本計劃將設計並實現一個能放置於耳道內（CIC/ITC, Completely-in-Canal/In-the-Canal）的完整助聽器系統。整個系統的體積要夠小，病人能直接放置於耳內。因為是以電池提供電力，系統要有極低的功率消耗，攜帶者才能長時間使用，而不會感覺不方便。好的助聽器系統通常須要具有可程式性，能根據不同使用者人不同的聽覺反應來調整系統參數。同時它還須要具有適應性，能在環境的變化下還能發揮最佳助聽功能。 在系統部分，本計畫將發展高階助聽器所須具備的各項功能，例如聽力補償策略、噪音抑制、回饋音消除等。補償策略是針對華語而設計，包括濾波器信號處理（Filtering Signal Processing）、頻譜整形（Frequency Shaping）、動態範圍壓縮（Dynamic Range Compression）等重要運算。針對噪音及回饋音之抑制，除了發展所需的信號處理技術之外，本計畫將以自行開發之助聽器載具及聲學元件來控制耳道內之音場，並依據實際量測數據建立模擬用之模型，同時也會開發具有自適應能力之方向性麥克風。 在硬體部分，本計畫將開發微機電式麥克風及喇叭來做聲學訊號與電學訊號之轉換。本計畫也將開發助聽器專用的 SoC 晶片，此晶片上有「助聽器計算引擎」，配合訊號處理加速器，可執行助聽器之所有運算。這些數位電路必須在功能、可程式性、及消耗功率之間取得平衡。晶片上也會包含類比介面電路，用來將麥克風接收的訊號轉成數位訊號，或將數位訊號轉成類比訊號並驅動喇叭。最後，本計畫會開發可以異質整合的微小型助聽器載具，可以整合聲學元件、晶片，及其他零件成完整之助聽器系統。 本計畫的所有電路，除了微機電麥克風及喇叭外，最後將整合於 90 nm CMOS 的單晶片中。以 1 V 電池操作，整體消耗功率不得超過 1 mW。另外，所發展的晶片都會以「晶片效能指標」（Chip Performance Index, CPI）來和功能類似的晶片相比較。而本計畫的目標就是追求最佳的 CPI。

This project is to design and realize a completely-in-canal/in-the-canal (CIC/ITC) hearing aid. The form size of the entire system must be small so that it can be placed inside a human ear. Since it is powered by a battery, the system must consume diminutive power for long-time usage. A good hearing aid needs be programmable for easy adjustment of system parameters so as to customize treatment of users of different auditory response. It also needs to be adaptable against environment variation to attain optimal hearing aid function. On the system level, we will develop all necessary functions of a high-end hearing aid, including advanced hearing loss compensation, noise reduction, and echo cancellation. The hearing loss compensation strategy will be specially developed for Chinese-speaking users. It involves signal processing operations such as filtering signal processing, frequency shaping, and dynamic range compression. In addition to signal processing techniques for noise reduction and echo cancellation, this project will control the in-the-canal acoustic field using the self-developed hearing aid carrier and acoustic components, and construct the corresponding model for simulation. And we will develop adaptive directional microphone system. This project will realize the entire hearing aid hardware. MEMS microphones and speakers are developed for conversion between acoustic and electrical signals. We will design a hearing aid SoC chip. The chip includes a computing engine and hardware accelerators that together perform all signal processing operations. The digital circuitry requires careful trade-off among functionality, programmability, and power dissipation. The SoC chip also integrates analog interface circuits that convert signals from microphones into digital form and convert digital signals into analog form to drive speakers. Finally, this project will develop a hearing aid carrier for heterogeneous integration of acoustic components, SoC chip, and other components to form a complete system. Except the MEMS microphones and speakers, all circuits will be integrated on a signal chip fabricated in a 90 nm CMOS technology. The total power consumption will be less than 1 mW. Circuits designed in this project will be compared with known designs of similar functions, using the Chip Performance Index (CPI). The goal of this project is to achieve the best CPI.