標題: 助聽器晶片及系統---子計畫六:助聽器類比介面電路(I)
Analog Interface Circuits for Hearing Aid SoC(I)
作者: 吳介琮
WU JIEH-TSORNG
國立交通大學電子工程學系及電子研究所
關鍵字: 低功率類比電路;混合訊號式積體電路;助聽器;Low-Power Analog Circuits;Mixed-Signal Integrated Circuits;Hearing Aids.
公開日期: 2007
摘要: <![CDATA[ 本計畫是「助è�½å™¨æ™¶ç‰‡å�Šç³»çµ±ã€�æ•´å�ˆåž‹è¨ˆåŠƒçš„一個å­�計畫。目的是設計å�Šå¯¦ç�¾æ­¤ç³»çµ±æ‰€éœ€è¦�的低功率混å�ˆè¨Šè™Ÿå¼�介é�¢é›»è·¯ï¼Œä¸¦ä¸”將與其他數ä½�電路整å�ˆæ–¼å�Œä¸€æ™¶ç‰‡ä¸Šã€‚本計劃將開發(1)微機電麥克風å‰�置放大器與類比數ä½�轉æ�›å™¨ï¼›ï¼ˆ2)微機電喇å�­é©…動電路;(3)電æº�控制電路。在麥克風接收端,訊號的頻寬有 20 kHz,而訊號的動態範åœ�(Dynamic Range)å�¯é«˜é�” 100 dB。雖然傳統的 Delta-Sigma ADC 有足夠的動態範åœ�,但也比較耗電。本å­�計劃將研究更有效率的類比數ä½�轉æ�›æ–¹æ³•ã€‚在喇å�­ç«¯çš„驅動電路將會是整個助è�½å™¨ç³»çµ±æœ€è€—電的部份。本å­�計劃將é…�å�ˆç‰¹æ®Šè¨­è¨ˆçš„微機電喇å�­ä»¥é«˜æ•ˆçŽ‡çš„æ–¹å¼�驅動。所有電路將加入自動調整功能,它能根據製程ã€�電壓ã€�溫度(Process, Voltage, Temperature, 簡稱 PVT)的變化自動調整功率消耗,因而能在所需的效能è¦�求下有最低的功率消耗。本計劃的電路設計將追求最佳功率效益。 本計畫的所有電路,除了微機電麥克風å�Šå–‡å�­å¤–,最後將整å�ˆæ–¼ 90 nm çš„ CMOS 單晶片中。以 1 V 電池æ“�作,類比電路的功率消耗ä¸�得超é�Ž 500 uW。å�¦å¤–,所發展的電路都會以「晶片效能指標ã€�(Chip Performance Index, CPI)來和功能類似的電路相比較。而本計畫的目標就是追求最佳的 CPI。#2; ]]>
<![CDATA[ This project is one of the sub-projects of the 「Hearing Aid SoC and System� project. The objective is to design and realize the essential low-power mixed-signal interface circuits, and then integrate those circuits with other digital circuits on the same chip. This project will develop (1) a MEMS microphone preamplifier followed by an analog-to-digital converter; (2) a MEMS speaker driver; and (3) supply control circuits. At the microphone end, the required signal bandwidth is 20 kHz and the dynamic range is as high as 100 dB. Although the conventional Delta-Sigma ADC can achieve the required dynamic range, it also demands premium power dissipation. We will develop a more power-efficient A/D technique. At the speaker end, the driver will consume most of the energy resource. We will work with the MEMS team to improve the power efficiency of the speaker system. All circuits will contain automatic adjustment mechanism in response to process, voltage, and temperature (PVT) variation. The goal is to achieve minimum power consumption while meeting the performance requirements. In this project, all circuit design will pursue the optimal power efficiency. Except the MEMS microphone and speaker, all circuits will be integrated on a signal chip fabricated in a 90 nm CMOS technology. Operating under a 1 V battery supply, the total power consumption for the analog circuits will be less than 500 uW. Circuits designed in this project will be compared with known designs of similar functions, using the Chip Performance Index (CPI). The goal of this project is to achieve the best CPI. ]]>
官方說明文件#: NSC96-2220-E009-036
URI: http://hdl.handle.net/11536/102933
https://www.grb.gov.tw/search/planDetail?id=1464419&docId=262492
顯示於類別:研究計畫